Forum Discussion

JonGoh's avatar
JonGoh
Icon for New Contributor rankNew Contributor
11 months ago

Configuration via Protocol (CvP) fail after loading the periphery image

Hi, May I know if this issue has been resolved in newer versions of the CvP driver? I am still facing CvP intermittent failing problems and was wondering whether there are other workarounds other th...
Configuration
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
11 months ago

Hi,


Please copy the "lspci -vv" and "uname -mrs" printout of the FPGA board. Please also provide the step you use to update the kernel.


Thanks.



  • JonGoh's avatar
    JonGoh
    Icon for New Contributor rankNew Contributor
    11 months ago

    Hi @JohnT_Intel ,

    01:00.0 Unassigned class [ff00]: Altera Corporation Device 09c4 (rev 01)
    Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Region 0: Memory at f0000000 (64-bit, prefetchable) [disabled] [size=4M]
    Region 4: Memory at f0400000 (64-bit, prefetchable) [disabled] [size=256K]
    Capabilities: [40] Power Management version 3
    Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)
    Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [70] Express (v2) Endpoint, MSI 00
    DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
    ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 75.000W
    DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
    RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
    MaxPayload 256 bytes, MaxReadReq 512 bytes
    DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
    LnkCap: Port #1, Speed 8GT/s, Width x8, ASPM not supported
    ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
    LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
    ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
    LnkSta: Speed 8GT/s (ok), Width x8 (ok)
    TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
    DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
    10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
    EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
    FRS- TPHComp+ ExtTPHComp-
    AtomicOpsCap: 32bit+ 64bit+ 128bitCAS+
    DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ OBFF Disabled,
    AtomicOpsCtl: ReqEn-
    LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
    LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
    Compliance De-emphasis: -6dB
    LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
    EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
    Retimer- 2Retimers- CrosslinkRes: Upstream Port
    Capabilities: [b0] MSI-X: Enable- Count=16 Masked-
    Vector table: BAR=0 offset=00100000
    PBA: BAR=0 offset=00180000
    Capabilities: [100 v2] Advanced Error Reporting
    UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
    UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
    UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
    CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
    CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
    AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
    MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
    HeaderLog: 00000000 00000000 00000000 00000000
    Capabilities: [148 v1] Virtual Channel
    Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
    Arb: Fixed- WRR32- WRR64- WRR128-
    Ctrl: ArbSelect=Fixed
    Status: InProgress-
    VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
    Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
    Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
    Status: NegoPending- InProgress-
    Capabilities: [174 v1] Alternative Routing-ID Interpretation (ARI)
    ARICap: MFVC- ACS-, Next Function: 1
    ARICtl: MFVC- ACS-, Function Group: 0
    Capabilities: [184 v1] Secondary PCI Express
    LnkCtl3: LnkEquIntrruptEn- PerformEqu-
    LaneErrStat: 0
    Capabilities: [46c v1] Data Link Feature <?>
    Capabilities: [d00 v1] Vendor Specific Information: ID=1172 Rev=0 Len=05c <?>

    apd@apd-pc1:~$ uname -mrs
    Linux 6.6.37+ x86_64

    Steps that I took to update the kernel (following the guide that you mentioned above):

    git clone https://github.com/altera-opensource/linux-socfpga

    cd linux-socfpga

    git checkout socfpga-6.6.37-lts

    cd /usr/src/linux-socfpga

    cp -v /boot/config-$(uname -r) .config

    make menuconfig

    - Set Altera CvP FPGA Manager and FPGA Manager DebugFS to *

    Make -j 12

    export INSTALL_MOD_PATH=/usr/src/linux-socfpga

    MODPATH="INSTALL_MOD_PATH=/usr/src/linux-socfpga"

    ARGS="$MODPATH"

    make $ARGS modules

    sudo make modules_install

    sudo make install

    grub-mkconfig

    cat /boot/grub/grub.cfg

    sudo cp /etc/default/grub /etc/default/grub.bak

    cat /etc/default/grub

    gedit/etc/default/grub

    sudo update-grub

    Hope this gives more insight to the problem.

    Thanks,

    Jon