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mtwieghr
New Contributor
New ContributorConfiguration CRC check (Arria V GX)
This is related to my other thread. Much of the background info is the same, but I thought separate threads would help avoid confusion. Our design (5AGXMB3G4) has a Nios II with an EPCS controller (...
FakhrulA_altera
Regular Contributor
Regular ContributorHi mtwieghr,
To locate the FPGA bitstream in flash, you can try refer to the .map file generated with the .jic, it shows where each component (SOF,etc) is placed.
From my understanding, the corruption detection for Nios code isn’t handled by FPGA crc. If needed, you can implement a simple checksum or CRC check in the Nios bootloader to validate integrity before jumping to the app. You can try check this document as example/reference:
Nios II Custom Instruction User Guide.
Hope this helps.
Regards,
Fakhrul
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