Configuration / Initialization issues CYCLONE III custom board

Hi,

We made our custom board with CYCLONE III FPGA (EP3C16Q240) and memories [SdRam, Nand flash and serial flash (ST's MT25P16)] with only few interfaces [VGA, SD Card and Ethernet]

The board has two JTAGs. Viz.,

1> JTAG_1 connects to the JTAG pins of FPGA - (JTAG mode of programming the FPGA)

2> JTAG_2 connects to the Serial flash Memory - (Active Serial device programming)

PFA the schematics of the JTAG circuitry. P6 and P5 are the JTAG_1 and JTAG_2 respectively.

We have two options to program the board

1: configuring fpga with .sof file via jtag

We generated a .sof file which performs a simple operation of toggling a GPIO pin in the FPGA.

We programmed the .sof file through JTAG_1 and the Quartus II programmer says "Ended Programming successfully". But FPGA didn't function as intended. But, we see the following things

a) conf_done pin of FPGA is becoming high after the successful configuration as expected. Meaning, the configuration of the FPGA is successful.

b) init_done pin of FPGA is not becoming high. The FPGA will enter into user mode for executing user code only after making this pin high.

There were couple of instances we saw the init_done pin going high and the intended GPIO was toggling as expected. But this scenario happens rarely and also the time it takes to enter into the user mode is too high [it takes around 4 mins]

2: configuring the fpga from the serial flash

We have two methods to achieve this

(i) Loading the serial flash with a .pof file via JTAG_2.

(ii) Loading the serial flash via FPGA with a .jic file using JTAG_1.

In both the above cases, FPGA picks up the configuration from the flash and boots up after a hard restart.

(i) loading the serial flash with a .pof file via jtag_2.

We haven't succeeded in this method yet. The programmer tool [Quartus II] says "Can't recognize the Silicon ID". In parallel, we are doing a custom board only with the serial flash for flashing.

(ii) loading the serial flash via fpga with a .jic file using jtag_1.

In this case, we use JTAG_1 to flash the serial device. JTAG configures the FPGA to write the configuration into the serial flash device. We are able to successfully write the data into the serial device.

After the data is written into the flash, we performed CRC verification. The tools says no CRC errors. We understand that the tool verifies the data inside the serial flash by reading it via the FPGA.

We also have instances, where we get CRC errors. But the probability is less.

After successful [no CRC error] write of serial flash, we hard reset the board, so that the FPGA can read the configuration data from the serial flash to configure itself. But we see the conf_done pin toggling [in the "re-configure after error" mode]; meaning configuration not successful, so it retries configuring.

When writing the data into the flash, we see a clean signal on the oscilloscope on the ADSI pin. We tapped the signal at P5 pin 7.

When the FPGA reads data from the flash, we see the waveform with lot of ripples. Tapped signals on both the flash pin and on the P5 pin 9.

With the above scenarios, we understand

(a) When directly configuring the FPGA, the FPGA is getting configured but rarely enters user mode after a long time.

(b) When configuring the FPGA via the serial flash, the FPGA is never getting successfully configured.

What are we missing here? Please advice.

Let me know if you need any further details reg this.