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Altera_Forum's avatar
Altera_Forum
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12 years ago

Configurable LUTs in Altera FPGAs

Hi,

I've used Xilinx CFGLUT5 primitive quite a lot. It allows runtime LUT reconfiguration. The documentation of cfglut5 is here (http://www.xilinx.com/itp/xilinx10/books/docs/virtex5_hdl/virtex5_hdl.pdf) on page 74.

This is a feature that saves lots of logic in certain kinds of circuits. For example pattern mask & matchers.

I couldn't find anything equivalent to that in Altera devices.

Does anybody know if any kind of LUT reconfiguration is supported by Altera ?

Thanks,

Evgeni

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Interesting. Never seen that before, but looks like a serial input into their CLBRAM function.

    I don't believe Altera FPGA's have such a thing. Could you use a LUTRAM to do something similar? I assume your block is bigger than 1 LUT, and hence a RAM should work similarly, you just have to control the addressing logic. (Do you currently do the CFGLUT from a processor?) It's not identical, but might work.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I guess it's possible to use LUTRAM for that purpose.

    I currently have custom logic that drives 1-bit low-speed signal thru the very long chain of the CFGLUT5. That custom logic is memory-mapped.