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Note that you don't actually need the address of your component's Avalon or AXI slave port. QSYS will assign the address when your component is put to use in a system. The HDL code for your component needs to be written as if starting at zero. The Avalon fabric will handle the address mapping.
In the event you are using the address of your component from the master port of another component, it is better to have that base address be programmable so that your components can be placed into systems without worrying about matching specific addresses.
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Thanks for the reply..
Yes, you are right that I should not worry about the addressing because it is handled by Avalon fabric. But I am using the base address of my Avalon Slave Port in a calculation to configure the DMA ( via another Avalon Master Port ).
I have an alternative by adding a register for base address in my HDL module which will be written by Nios Processor. But if I am able to get that address in the Validation or Elaboration phase of Qsys then its a great !!
Regards,
Harsh.
Honored Contributor
