complete bypass the PCS in GIGE Mode

Page 1-7 in volume 2 of the Stratix II GX Device Handbook states:

Receiver Phase Compensation FIFO Buffer

Each receiver data path has a dedicated phase compensation FIFO buffer

that decouples phase variations between the FPGA and transceiver clock

domains. this block is always used and cannot be bypassed.

This block alone cannot be taken out. The minimum latency before you can get your hands on the received data is 4 clock cycles (depending on the protocol you are using).

Jake