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Honored Contributor
Honored Contributorcomplete bypass the PCS in GIGE Mode
hey there, The question i can't figure out by reading the manual of the stratix II gx is, wether i can grab receivedata directly at the deserializer of the PMA. I want to leave out the complete...
Altera_ForumHonored Contributor
Honored ContributorPage 1-7 in volume 2 of the Stratix II GX Device Handbook states:
Receiver Phase Compensation FIFO Buffer Each receiver data path has a dedicated phase compensation FIFO buffer that decouples phase variations between the FPGA and transceiver clock domains. this block is always used and cannot be bypassed. This block alone cannot be taken out. The minimum latency before you can get your hands on the received data is 4 clock cycles (depending on the protocol you are using). Jake
