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Altera_Forum's avatar
Altera_Forum
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13 years ago

Compilation Report

In my compilation report I have

Total logic elements 5,036 / 24,624 ( 20 % )

Total combinational functions 4,228 / 24,624 ( 17 % )

Dedicated logic registers 3,216 / 24,624 ( 13 % )

For a

Family Cyclone III

Device EP3C25F324C6

So how do you get 5,036 out of 24,624 logical elements used when there are

1) 4,228/24,624 combinational functions used

PLUS

2) 3,216/24,624 dedicated logic registers

?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Not every register is driven by a LUT, and hence placed in its own logic element. You probably have 2,408 LUT+Reg going into Logic Elements, 1,820 LUT-only Logic Elements, and 808 register-only Logic Elements.

    I don't remember exactly, but don't think the CIII report estimates what the area would be if you tried packing unrelated registers and LUTs. This naturally can hurt performance though. Try putting the design into a quick LogicLock Region, say 3,500 logic elements in size, and see if it fits. If it doesn't, make it bigger. If it does, try smaller. And keep an eye on the performance.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you.

    The design fits however I am just trying to understand the compilation report. I am using the NEEK board and want to migrate to the first prototype so I am trying to identify an appropriate device from the resources used.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I also suggest you compile to the target device if you can before you spin the board. That way, you should have worked out any gotcha's like pin placement limitations, or other resource limitations you may not think about. (for example M9K blocks)

    Often you may find designs that use many more M9K's than % memory bits utilized may indicate. So if you go just my number of bits available, you may fool yourself into thinking it will fit when it doesn't.

    Also as you get into higher utilization, the tool has less flexibility in placement, due to congestion, so you may find you may not be able to meet timing for a design with high utilization vs a the same design in a part with lots of LE's available.

    Pete