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MRavi1's avatar
MRavi1
Icon for New Contributor rankNew Contributor
7 years ago

Compilation error in pipemult project.

Error (275021): Illegal wire or bus name " " of type signal

Error (12153): Can't elaborate top-level user hierarchy

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings

Can anyone please help me understand what exactly I should do to rectify it?

5 Replies

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    Check the connections of clock,wren(need to be wire) of ram instance & PRN, CLRN should connect inputs using pin tool.

    please let me know if you have any different concern.

    Regards,

    Vicky

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    Just to explain a bit clearer, you have clock and wren connected as busses (thick lines) instead of individual wires (thin lines). Delete the busses and use the wire tool to make the connections. Also, the reset input into the register (CLRN) should be hooked up as well, either to an I/O pin or perhaps even just pulled high.

    #iwork4intel

    • MRavi1's avatar
      MRavi1
      Icon for New Contributor rankNew Contributor
      7 years ago

      Yes. I tried that too, I just had some problems with installation. Once I re-installed the software it worked fine. Thanks !

  • NSola3's avatar
    NSola3
    Icon for New Contributor rankNew Contributor
    6 years ago

    Can you share the source codes files for this or link for the same?