MRavi1New Contributor6 years agoCompilation error in pipemult project. Error (275021): Illegal wire or bus name " " of type signal Error (12153): Can't elaborate top-level user hierarchy Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 2 warn...Show More
Vicky1Regular Contributor6 years agoHi,Check the connections of clock,wren(need to be wire) of ram instance & PRN, CLRN should connect inputs using pin tool. please let me know if you have any different concern.Regards,Vicky
Recent DiscussionsAvalon-ST configuration with Agilex 3 failsCyclone IV E – PLL Power Track Width Recommendation ClarificationOperating temperature for 10M08DCF256A7GSystem PLL of Agliex5 PCIE example design cannot be locked after configurationDownload links not working