compilation Error (10818): Can't infer register ...

Question

hi all,im trying to build a stopper using vhdl, modelsim and quartus.i wrote the vhdl code and tried it on modelsim and everything was just fine, the compilation and sim were good, as i expected.when i tried to compile it on quartus it gave me errors. im trying to understand how to fix it for more than 5 hours. please help me.the errors are:Code:Info: *******************************************************************Info: Running Quartus II Analysis &amp; Synthesis    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition    Info: Processing started: Sun Dec 23 22:11:21 2012Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stopper_new -c stopper_newInfo: Found 2 design units, including 1 entities, in source file stopper.vhd    Info: Found design unit 1: STOPPER-arc_stopper    Info: Found entity 1: STOPPERInfo: Found 1 design units, including 1 entities, in source file timer.bdf    Info: Found entity 1: timerInfo: Elaborating entity "timer" for the top level hierarchyWarning: Using design file hexss.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project    Info: Found design unit 1: hexss-arc_hexss    Info: Found entity 1: hexssInfo: Elaborating entity "hexss" for hierarchy "hexss:inst2"Info: Elaborating entity "STOPPER" for hierarchy "STOPPER:inst"Warning (10492): VHDL Process Statement warning at stopper.vhd(70): signal "cnt_sec" is read inside the Process Statement but isn't in the Process Statement's sensitivity listWarning (10492): VHDL Process Statement warning at stopper.vhd(71): signal "cnt_sec" is read inside the Process Statement but isn't in the Process Statement's sensitivity listWarning (10492): VHDL Process Statement warning at stopper.vhd(72): signal "sec" is read inside the Process Statement but isn't in the Process Statement's sensitivity listWarning (10492): VHDL Process Statement warning at stopper.vhd(73): signal "sec" is read inside the Process Statement but isn't in the Process Statement's sensitivity listWarning (10492): VHDL Process Statement warning at stopper.vhd(74): signal "min" is read inside the Process Statement but isn't in the Process Statement's sensitivity listWarning (10492): VHDL Process Statement warning at stopper.vhd(75): signal "min" is read inside the Process Statement but isn't in the Process Statement's sensitivity listWarning (10631): VHDL Process Statement warning at stopper.vhd(25): inferring latch(es) for signal or variable "flag", which holds its previous value in one or more paths through the processError (10818): Can't infer register for "min[0]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[0]" at stopper.vhd(25)Error (10818): Can't infer register for "min[1]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[1]" at stopper.vhd(25)Error (10818): Can't infer register for "min[2]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[2]" at stopper.vhd(25)Error (10818): Can't infer register for "min[3]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[3]" at stopper.vhd(25)Error (10818): Can't infer register for "min[4]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[4]" at stopper.vhd(25)Error (10818): Can't infer register for "min[5]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[5]" at stopper.vhd(25)Error (10818): Can't infer register for "min[6]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[6]" at stopper.vhd(25)Error (10818): Can't infer register for "min[7]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[7]" at stopper.vhd(25)Error (10818): Can't infer register for "min[8]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[8]" at stopper.vhd(25)Error (10818): Can't infer register for "min[9]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[9]" at stopper.vhd(25)Error (10818): Can't infer register for "min[10]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[10]" at stopper.vhd(25)Error (10818): Can't infer register for "min[11]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[11]" at stopper.vhd(25)Error (10818): Can't infer register for "min[12]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[12]" at stopper.vhd(25)Error (10818): Can't infer register for "min[13]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[13]" at stopper.vhd(25)Error (10818): Can't infer register for "min[14]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[14]" at stopper.vhd(25)Error (10818): Can't infer register for "min[15]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[15]" at stopper.vhd(25)Error (10818): Can't infer register for "min[16]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[16]" at stopper.vhd(25)Error (10818): Can't infer register for "min[17]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[17]" at stopper.vhd(25)Error (10818): Can't infer register for "min[18]" at stopper.vhd(49) because it does not hold its value outside the clock edgeInfo (10041): Inferred latch for "min[18]" at stopper.vhd(25)Error: Can't elaborate user hierarchy "STOPPER:inst"Error: Quartus II Analysis &amp; Synthesis was unsuccessful. 20 errors, 8 warnings    Info: Allocated 199 megabytes of memory during processing    Error: Processing ended: Sun Dec 23 22:11:22 2012    Error: Elapsed time: 00:00:01Error: Quartus II Full Compilation was unsuccessful. 20 errors, 8 warningssee attached for the codeim a novice with vhdl so i would appreciate any help. thanks

altera_forum · Answer

for synthesis style vhdl you need to adhere to clocked process template like the second one of yours. The first process assigns clock edge after lots of if/elsif which is not allowed by synthesis tools(otherwise not wrong). All signal assignments inside clocked process infer registers and you are allowed either to start with

if clock edge...

or with reset then elsif clock edge... nothing extra on top.

Additionally you can just use: wait until clock = '1'; without any ifs.

altera_forum · Answer

The problem is here      if resetN = '0' then 
        cnt_sec     &lt;= 0;
        sec     &lt;= 0;
        min      &lt;= 0;
        flag := 1;
        
    elsif stopN = '0' then
        flag := 1;
    elsif startN = '0' then
        flag := 0;
    end if;
        
    if rising_edge(CLK) then  Must be changed to something like below to be synthesizable.     if resetN = '0' then 
        cnt_sec     &lt;= 0;
        sec     &lt;= 0;
        min      &lt;= 0;
        flag := 1;
    elsif rising_edge(CLK) then  The start and stop action should be done in a synchronous way.  By the way, every "similar thread" below is talking about the same problem.

altera_forum · Answer

thank you, how can i do the stopN and startN in a synchronous way?

altera_forum · Answer

signal flag;
--
process (CLK,
--        
  elsif rising_edge(CLK) then
    if stopN = '0' then
      flag &lt;= 1;
    elsif startN = '0' then
        flag &lt;= 0;
    end if;

altera_forum · Answer

thank you very much!

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compilation Error (10818): Can't infer register ...

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