Hi, I have several FIFO's and i need to read out, the one with the most data first. I use the byte counter of the fifo to compare. But what is the best way to compare those vectors? if A > B and A > C and A > D then input <= A elsif B > A ...... You get the point* Or is there a better way ? For now i'm using above code but it is getting complex with allot of fifo's.

Sounds excessive logic will be needed. I am not sure about the need to do that in your case (I assume your work is video based from previous posts). Consider waiting until all fifos have some minimum data size then read out all on same clock.

--- Quote Start --- (I assume your work is video based from previous posts) --- Quote End --- True, But i need the images to be stored at the same time in one memory. Can't buffer a whole image in BlockRam, so i buffer in FIFO's first. Then i write the fifo with the most data into the memory untill that one is empty. Then i go one with the next one. Reading the fifo's at the same time (like u suggested) would imply parrallel writing to the memory what isn't possible in my case. (well it's possible to write 2 bytes at one time but it would be to the same adress)

consider setting a queue flag for each fifo; flag to be raised when it has a reached a given size then pass it to memory and lower flag followed by next fifo in the queue and so on.

Thx i'll consider it. But also if there are two bytes in the fifo they need to be send to the memory (if all other fifo's are empty)

Another approach: Library IEEE; use IEEE.Std_Logic_1164.all; use IEEE.numeric_std.all; entity idxmaximum is port ( Clk : in std_logic ; A : in std_logic_vector(7 downto 0) ; B : in std_logic_vector(7 downto 0) ; C : in std_logic_vector(7 downto 0) ; D : in std_logic_vector(7 downto 0) ; MaximumValue : out std_logic_vector(7 downto 0) ; MaximumIndex : out std_logic_vector(1 downto 0) ) ; end idxmaximum ; architecture a of idxmaximum is type idxval is record isvalue : natural ; idx : natural ; end record idxval ; type array_idxval is array (natural range <>) of idxval ; function subarray_idxval( src : array_idxval ; idx_from , idx_downto : natural ) return array_idxval is variable r : array_idxval ( idx_from - idx_downto downto 0) ; begin for i in 0 to idx_from - idx_downto loop r(i) := src(idx_downto + i) ; end loop ; return r ; end function subarray_idxval ; function maximum ( src : array_idxval ) return idxval is variable a , b : idxval ; begin if (src'length = 2) then a := src(0) ; b := src(1) ; elsif (src'length = 3) then a := src(0) ; b := maximum(subarray_idxval(src , 2 , 1) ); else a := maximum(subarray_idxval(src , src'length / 2 - 1 , 0)) ; b := maximum(subarray_idxval(src , src'length - 1 , src'length / 2)) ; end if ; if (a.isvalue < b.isvalue ) then return b ; else return a ; end if ; end function ; signal la , lb , lc , ld : std_logic_vector(7 downto 0) ; signal abcd : array_idxval(3 downto 0) ; signal maxresult : idxval ; begin abcd(0).isvalue <= to_integer( unsigned( la )) ; abcd(0).idx <= 0 ; abcd(1).isvalue <= to_integer( unsigned( lb )) ; abcd(1).idx <= 1 ; abcd(2).isvalue <= to_integer( unsigned( lc )) ; abcd(2).idx <= 2 ; abcd(3).isvalue <= to_integer( unsigned( ld )) ; abcd(3).idx <= 3 ; process( Clk ) begin if rising_edge( Clk ) then la <= A ; lb <= B ; lc <= C ; ld <= D ; maxresult <= maximum( abcd ) ; end if ; end process ; MaximumValue <= std_logic_vector( to_unsigned( maxresult.isvalue , 8 ) ) ; MaximumIndex <= std_logic_vector( to_unsigned( maxresult.idx , 2 ) ) ; end a ; This scales easily to any number of fifo's, and will be faster than the if-then-elsif approach. You can use the MaximumIndex result to select the fifo to process. The MaximumValue tells you how many you can do for that fifo. I registered both the input and output of the module, just to find out how fast it will run, the function 'maximum' itself results in a fully combinatorial circuit.

Forum Discussion

Altera_Forum

Honored Contributor

15 years ago

compare multiple std_logic_vectors

Hi,

I have several FIFO's and i need to read out, the one with the most data first. I use the byte counter of the fifo to compare.

But what is the best way to compare those vectors?

if A > B and A > C and A > D then

input <= A

elsif B > A ......

You get the point*

Or is there a better way ?

For now i'm using above code but it is getting complex with allot of fifo's.

11 Replies

Altera_Forum
Honored Contributor
15 years ago
Sounds excessive logic will be needed. I am not sure about the need to do that in your case (I assume your work is video based from previous posts). Consider waiting until all fifos have some minimum data size then read out all on same clock.

Forum Discussion

compare multiple std_logic_vectors

11 Replies

Recent Discussions

Schematics/layout for TerasIC SoCKit rev. D with Cyclone V

which A3C devices have on chip decoupling capacitors

Cyclone IV drop in replacement confirmations

Agilex 3 PLL in Source Synchronous mode ?

Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)