Coding style to minimize combinational path delay?

Unfortunately, it is too slow for running my design at 125 MHz. Perhaps not Cyclone IV specific. Anything can be pipelined but it will fragment an otherwise straight-forward design into a jumble of flip-flops impossible to understand. Pipelining is suitable for some designs where it makes architechural sense but, unfortunately, it did not make sense in my design - lowering the clock frequency to 62.5 MHz and possibly widening certain data buses from 8 to 16 (or 32) bits made more sense in my case.