Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCoding style to minimize combinational path delay?
I'm tuning my logic to meet timing. I have a long continuous assignment statement that outputs a signal based on the current state in my FSM. The below implementation results in a long mux chain. Is ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Thanks all for your suggestions. I ended up cutting my clock frequency in half, giving me much more head room. The Cyclone IV is simply too slow (i.e. too much combinational path delays). In case I can't meet my data throughput target (border-line now) then I will have to double the width of the critical data path in my design. --- Quote End --- The Cyclone IV isn't that slow. I have a design with 200 MHz and 150 MHz (among others) clock frequencies in a EP4CE40F23C7N device. I have similar muxes in the 150 MHz domain (switching constants for multipliers). Proper pipelining is key - divide and conquer!
