Coding style to minimize combinational path delay?

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I just want to point out, in contrast to multiple comments in this thread, that case statements are inherently supposed to have priority. They are not supposed to execute all branches in parallel. Don't take my word for it, though; take it from someone who trains Verilog professionally:

http://sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html

"Compares the net, register or literal value to each case and executes the statement or statement group associated with the first matching case."

I have found this to be a point of contention across different tools. If you want to make sure that the branches of a case statement execute in parallel, look into the "unique" key word from SystemVerilog.

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You are absolutely correct, that was a bit of a blanket statement on my part. I have never coded using a case statement that could potentially have priority like you mentioned so it slipped my mind.