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If you examine the TQ diagram you see that the code shown in post 1 is only half the data path and second that 66% of the data path is Interconnect delay.
The code shown only takes two hops, although it is a lot of typed text it is a rather simple 'mux' and the compiler can optimize heavily (given that the 'mux' inputs are mostly constants).
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So, in other words, there's not much room for improvement by changing the statement? This seems to be in line with my earlier attempts to change into a case statement.
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The high ratio of interconnect makes me think your FPGA is getting full?
Can I suggest to put a pipeline register between the resp. outputs of main_controller_inst and the input of tx_tlp_buffer_inst?
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How can i find out whether the interconnects are getting crowded?. Only 18% of the total logic elements are used, accordingly to the compilation report.
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Can I suggest to put a pipeline register between the resp. outputs of main_controller_inst and the input of tx_tlp_buffer_inst?
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This seems to be a good idea. I intended need to convert the receiving reg[] based 'memory' into a true M9K RAM-based memory anyways. The M9K-based RAM generated by the MegaWizard has all inputs registered so will pipeline the offending path.
It seems now is a good time to do it.
Honored Contributor
