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Altera_Forum
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13 years ago

Clocking External SRAM with FPGA Output

Hi all,

I'm working on a design for a Cyclone IV GX that will be using an external pipelined SRAM chip. I've been searching quite a bit, but maybe I'm using the wrong search terms; What port should I use on the FPGA to clock the SRAM? My board's clock will be running at half the speed of my HDL design, which will use a PLL on the FPGA to generate the correct clock. This generated clock will also be used to clock the external SRAM.

Should I use the dedicated clock output pin of the PLL I will be using to clock the SRAM? In that case what mode should I run the PLL in?

Or should I just use a regular I/O pin? I'm worried that the dedicated clock output will have a different delay than the I/O pins that will drive the address/data/control signals, and cause problems.

Any help is appreciated.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I guess, pipelined SRAM chip means Synchronous SRAM? Using a dedicated clock output would be the standard solution for easy timing closure, outputting the same clock that drives the RAM interface. But clock through IO pin can work as well, as long as you don't work at the SRAM speed limit. You get additional clock skew which substracts from the SRAM's timing margin.

    In any case, you should constrain the SRAM interface signals according to the timing specification of the chip. If done correctly, Quartus will care for correct timing respective tell you if it can't guarantee it under the given conditions.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    I guess, pipelined SRAM chip means Synchronous SRAM? Using a dedicated clock output would be the standard solution for easy timing closure, outputting the same clock that drives the RAM interface. But clock through IO pin can work as well, as long as you don't work at the SRAM speed limit. You get additional clock skew which substracts from the SRAM's timing margin.

    In any case, you should constrain the SRAM interface signals according to the timing specification of the chip. If done correctly, Quartus will care for correct timing respective tell you if it can't guarantee it under the given conditions.

    --- Quote End ---

    Thanks FvM,

    Yes, it is Cypress synchronous SRAM, unfortunately I can't remember the part number off the top of my head.

    I will use the dedicated clock output, but what is the recommended mode for the PLL for this type of application? I do not know whether to use Zero Delay Buffer, Normal, or no compensation. The device handbook explains them well, but it's not clear to me which should be used in this instance.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The different PLL modes are only relevant for relation of PLL generated clock to clock input. If you use the same PLL clock to drive both the RAM interface and the clock output, the PLL mode is irrelevant. In special cases, a phase shift between the internal and external clock might be considered, but it's still independent of the PLL mode. Nevertheless, I would use normal mode in case of doubt.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    The different PLL modes are only relevant for relation of PLL generated clock to clock input. If you use the same PLL clock to drive both the RAM interface and the clock output, the PLL mode is irrelevant. In special cases, a phase shift between the internal and external clock might be considered, but it's still independent of the PLL mode. Nevertheless, I would use normal mode in case of doubt.

    --- Quote End ---

    Thank you for clearing that up, FvM.

    I had been thinking about it before and was even considering using 2 PLLs, one in Zero Delay Buffer mode for the SRAM, and one in Normal mode for the interface so that the phase would be aligned for both, but it sounds like that is unnecessary.