Clocking External SRAM with FPGA Output

I guess, pipelined SRAM chip means Synchronous SRAM? Using a dedicated clock output would be the standard solution for easy timing closure, outputting the same clock that drives the RAM interface. But clock through IO pin can work as well, as long as you don't work at the SRAM speed limit. You get additional clock skew which substracts from the SRAM's timing margin.

In any case, you should constrain the SRAM interface signals according to the timing specification of the chip. If done correctly, Quartus will care for correct timing respective tell you if it can't guarantee it under the given conditions.