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Honored Contributor
Honored ContributorClocking External SRAM with FPGA Output
Hi all, I'm working on a design for a Cyclone IV GX that will be using an external pipelined SRAM chip. I've been searching quite a bit, but maybe I'm using the wrong search terms; What port s...
Altera_ForumHonored Contributor
Honored ContributorThe different PLL modes are only relevant for relation of PLL generated clock to clock input. If you use the same PLL clock to drive both the RAM interface and the clock output, the PLL mode is irrelevant. In special cases, a phase shift between the internal and external clock might be considered, but it's still independent of the PLL mode. Nevertheless, I would use normal mode in case of doubt.
