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I guess, pipelined SRAM chip means Synchronous SRAM? Using a dedicated clock output would be the standard solution for easy timing closure, outputting the same clock that drives the RAM interface. But clock through IO pin can work as well, as long as you don't work at the SRAM speed limit. You get additional clock skew which substracts from the SRAM's timing margin.
In any case, you should constrain the SRAM interface signals according to the timing specification of the chip. If done correctly, Quartus will care for correct timing respective tell you if it can't guarantee it under the given conditions.
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Thanks FvM,
Yes, it is Cypress synchronous SRAM, unfortunately I can't remember the part number off the top of my head.
I will use the dedicated clock output, but what is the recommended mode for the PLL for this type of application? I do not know whether to use Zero Delay Buffer, Normal, or no compensation. The device handbook explains them well, but it's not clear to me which should be used in this instance.
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