Forum Discussion
New ContributorClock switchover on CycloneV PLL
Yes, if based on this internal message:
It would take 2-3 clock cycles to detect the stopped clock , another 2-3
clock cycles to complete the switch and a couple of cycles extra until the PLL achieves lock.
New ContributorHi ShengN_altera thanks for your reply.
"...the circuit automatically switches to the backup clock in a few clock cycles and updates the status signals, clkbad and activeclk"
This means that input circuit needs some clock cycles to detect that one of the input is now missing: fine. In consequence of that event, do the PLL outputs also stops working for the same amount of clock cycles?
For better understanding, the two input clocks have the same frequency.
- ShengN_altera
Super Contributor
Yes, if based on this internal message:
It would take 2-3 clock cycles to detect the stopped clock , another 2-3
clock cycles to complete the switch and a couple of cycles extra until the PLL achieves lock.- aerdna
ShengN_altera : thanks for the clarification, is there any documentation clarifying all this information? (also about the locked behavior)
Does the locked signal from the PLL behave accordingly?
- ShengN_altera
It would take 2-3 clock cycles to detect the stopped clock: This is not mentioned in the document.
another 2-3 clock cycles to complete the switch: This is mentioned in https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/ip-core-parameters-clock-switchover-tab.html the circuit automatically switches to the backup clock in a few clock cycles
a couple of cycles extra until the PLL achieves lock: This is mentioned in https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/pll-lock.html The number of cycles required to gate the lock signal depends on the PLL input clock which clocks the gated-lock circuitry. Divide the maximum lock time of the PLL by the period of the PLL input clock to calculate the number of clock cycles required to gate the lock signal. The Max Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) is 1 ms based on this https://www.intel.com/content/www/us/en/docs/programmable/683801/current/pll-specifications.html
