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aerdna's avatar
aerdna
Icon for New Contributor rankNew Contributor
9 months ago
Solved

Clock switchover on CycloneV PLL

Hello all, In a cyclone V device, I'm using  a PLL supporting the automatic switchover with manual override.  On the 2x clock output, I observe a jump of 2 clock cycles whenever there's a switchove...
Programmable Logic Device
  • ShengN_altera's avatar
    ShengN_altera
    9 months ago

    Yes, if based on this internal message:

    It would take 2-3 clock cycles to detect the stopped clock , another 2-3
    clock cycles to complete the switch and a couple of cycles extra until the PLL achieves lock.

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
9 months ago

Please ignore previous post, check this link the PLL circuitry monitors the selected reference clock. If one clock stops, the circuit automatically switches to the backup clock in a few clock cycles and updates the status signals, clkbad and activeclk.

Based on the internal message, those few clock cycles can't be avoided and usually take about 2-3 cycles.