Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity of data and clock recovery). From this data there are recovered 125 MHz pulses every 44.1 kHz (sync pulses). I would like to recover this 44.1 kHz clock from the bit stream. (for audio purposes - to match the clock of the data - if internal 44.1 clock is used form the generator there are some bad effects in the sound). My questions are: 1) Can i simply feed those pulses into the second PLL module to recover the data ? 2) Are there any other considerations that i should think about ? thanks madness123

The bitstream encoding details aren't very clear in your post. But generally speaking, regular Altera PLLs aren't designed for CDR purposes. They require a continuous reference clock to synchronize on it. Depending on required clock tolerance, there may be a chance to implement a CDR scheme based on PLL dynamic phase shift in user logic. Newer FPGA families with hardware SERDES are also implementing a software CDR feature.

Hi FvM, The Clock and Data Recovery works fine, perhaps it's not done with best practises but it works with no problems. I have the question about pulses that are generated from this data (their source doesn't really matter) -> can i recover a clock from pulses occuring approx. every (1/44100)s. best regards madness

As far as I understand, the 125 MHz is already recovered from the data stream. Then the 44.1 kHz detection problem hasn't to do with clock recovery, it's about detecting a sync pattern. What's specific to the 44.1 kHz pattern that allows to distinguish it from the data stream? By the way, what's the involved FPGA family

If I understood you, you already have pulses at 44.1KHz possibly generated from a counter or sync pulse. You want to generate 44.1KHs from data itself. I suggest you use simple averaging filter(just accumulator) to remove high frequency. i.e. add up samples for some suitable total that will build up then come down to zero as the stream stops at zero. You should then get sort of triangular pulses at 44.1KHz then apply a comparator to get cleaner pulses.

Hi, the family is Cyclone III - 5k LE. As kaz has written i already have 44.1k sync pulses from data itself. I put the data bits into the shift register, and then: sync_detect : process (clk_125_in, shift_register) begin if clk_125_in'event and clk_125_in = '1' then if ((shift_register(14 downto 5) = "1100010001") and (shift_register(4 downto 0) /= "11000")) THEN synchronized <= '1'; else synchronized <= '0'; end if; end if; end process sync_detect; So my questions are once again :). 1) From the data i get synchronized pulses every 44.1kHz. I would like to and have to make a clock from this, I even would have to if neccessary multiply it by 2 or 4 to get 88.2 or 176.4k for different modes. That's why i'm thinking about PLL. Can i simply put them in the PLL or should i do smth with them as kaz has written. 2) I had ocasionally problems with fan-outing this signal to the other parts of my design - i suppose that due to CDR there were some problems. Could i simply put there another signal like synchronized2 to double up the logic, but to get the second signal and not to mess with the synchronized? Or am i saying stupid things?:) best regards

Clock recovery from signle 125MHz pulses with PLL

25 Replies

Altera_Forum
Honored Contributor
13 years ago
The sophisticated functionality offered with the NCO core is the resource saving way to generate high resolution sine waves. A basic digital NCO as required for a ADPLL isn't more than a simple phase accumulator, involving a few lines of HDL code. The method is explained in the NCO user manual. Also low and medium resolution sine generators can be easily implemented without referring to the Altera core if you don't have a Quartus subscription license.
Altera_Forum
Honored Contributor
13 years ago
Hi,
thanks FvM,
best regards
madness
Altera_Forum
Honored Contributor
13 years ago
I opened megafunction wizard and found NCO. Are there any restrictions to using this megafunction ?
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Yes you need to pay a license for it, or use it in evaluation mode (i.e. with the USB blaster connected all the time, and you can't flash your project)
--- Quote End ---

So as long as your USB-Blaster is connected, you can play with it.

best regards
Altera_Forum
Honored Contributor
13 years ago
yes. You'll see a window after you configure the FPGA saying you are in evaluation mode. Don't close this window and you can use the NCO. It will stop working when you close the window, or after a certain delay (1 hours IIRC) if you disconnect the USB blaster.

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Clock recovery from signle 125MHz pulses with PLL

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