Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Clock problem

Hi All, I am trying to reduce the clock frequency from 25 MHZ to 12.5 MHZ using VHDL. I also intend to implement this in hardware, however I am having a lot of difficulty with my c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

sir your code is not working

Error (10482): VHDL error at clk200.vhd(2): object "std_logic" is used but not declared

--- Quote End ---

You still need to put in at the top: library ieee; use ieee.std_logic_1164.all

In regard to this discussion, I'm surprised no one mentioned it, but I'd really design this as a module with 2 free-running counters that trigger each other; one to generate the "start" pulse at 1 Hz, and the other to generate the "long" pulse. Thinking of these as clocks just isn't a good idea.