Clock problem

Hi All,

I managed to get the following code working after I initially had some problems in declaring variables and generally not understanding the code.

I have hardware on which there is a 25 MHZ crystal oscillator and I have reduced that frequency to 1 HZ. It worked on the simulator and on the hardware as I assigned the output to an LED. Cris kindly posted me some code and I thought it would be more beneficial for my progress I continued with mine. I have a couple of questions.

1) Is my code OK,

2) Is this the correct way to approach the problem, I have tackled it more as a software problem and VHDL is a hardware language. Would it be more proper for me to create divide by 2 counters in vhdl in order to reduce frequency.

Thank you in advance for your help.

My code

-- Standard libary delarations

library ieee;

use ieee.std_logic_1164.all;

-- define input and outputs for the entity

entity led is port(

clk_in: in std_logic;

clk_out: buffer std_logic;

clk: buffer std_logic);

end led;

-- internal function of enetity

architecture behave of led is

--internal variable

signal count : integer :=1;

begin

process (clk_in,clk_out)

begin

-- Required in order to convert the sinewave to a square wave

clk_out <= not clk_in;

-- Check for rising edge of clock

if(clk_out'event and clk_out='1') then

--increment the count variable by 1

count <=count+1;

-- when count is 2

if(count = 1250000) then

clk <= not clk;

count <= 1;

--assign 1 to the variable which will be assigned to an output pin

end if;

end if;

end process;

end behave;