Altera_Forum
Honored Contributor
15 years agoclock mux with internally generated inputs
I generated a clock mux using altclkctrl megawizard. My input signals, both the clocks and select signal are generated internally. They are not coming from the clock pin or PLL. The quartus tool complains that the inputs should come from either the clock pin or PLL. How to work around this issue? I am porting my xilinx FPGA design to altera. In xilinx, I used BUFGMUX to do this.