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Altera_Forum's avatar
Altera_Forum
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15 years ago

clock mux with internally generated inputs

I generated a clock mux using altclkctrl megawizard. My input signals, both the clocks and select signal are generated internally. They are not coming from the clock pin or PLL. The quartus tool comp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your reply. I am dynamically switching clocks. Do you have an example verilog code for glitch free clock mux? Also, do I need to take care of any special timing issues? I am doing an ASIC prototyping and I have to use 8 of these muxes in different places.