New Contributor
ContributorTo have a reliable recovery lock after disturbed input clock, users can enable self-reset by setting the "Enable self-reset on lost lock in PLL" option.
LVDS SERDES Transmitter/Receiver IP Cores User Guide mentions of this option,
'Enable self-reset on lost lock in PLL':
Turn on this option to reset the PLL automatically whenever the PLL loses lock.
This option is available only for Arria II GX, Arria II GZ, HardCopy III, HardCopy IV, Stratix III, and Stratix IV
devices when SERDES is implemented in logic cells, and for Cyclone lll, Cyclone IV, and Intel Cyclone 10 LP devices.
New ContributorHello,
Actually I am using Arria 10 GX and also my problem is not PLL losing lock, it never get locked from the beginning. How much jitter I can apply in simulation?
