Clock group vs. clock false path

Your reset if generated in a different clock domain need to be synchronised by two stage registers before using it in another clk domain. Then you can apply false path on both synchronisers. applying clk groups or cut path betwen clocks implies first synchroniser only which is over zealous.

By the way let me reword my previous post.

For occasionally changing signals such as software commands or reset ...etc. it is possible to set false path if that is going to help timing(irrespective of clk domain change). The false paths must be on the synchroniser registers and not beyond.