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Altera_Forum's avatar
Altera_Forum
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15 years ago

Clock group vs. clock false path

I have a couple of clocks coming in that are not related to each other. Before I put them in a group, I ran TimeQuest and it was complaining about some setup slack violation. I know I should have u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

All of my resets are handled asynchronously; i.e.

always @(posedge clock or negedge reset_n)

begin

if (!reset_n)

...

else

...

end

Now, granted that reset_n is not an input pin. It is generated from a counter -- basically after the FPGA is programmed, the reset_n is held low for a number of clocks before it is release.

Do you still see issues with the reset_n as implemented here?