Clock group vs. clock false path

If timequest knows some clks are unrelated then it should not care about the register timing violations across the interface between those clks.

It is up to you then to transfer signals across safely i.e. two stage synchronisers. If you are using dc fifos then that implies two stage synchronisers.

The idea is that unrelated clks will suffer violations inevitabley but you absorb them through two stage synchronisers.

Apart from unrelated clks, you may also add false path to other signals that change state occasionally e.g. system setup values from software(provided you use synchronisers on them whether they change clk domain or not). This may help lessen the burden on timing closure.

If timequest reports violations then it will be those within one clk domain.