Honored ContributorThank you, how i do? this is a way to learn . I have a project or I do PRODUCING A synchronous clock generator using Altera CPLD max3, ie from an input clock I must have output frequencies 8kHz output and 256 kHz and I think I can utiliset altpll of Quartus (megawizard) but I also need the VHDL code and testbench to simulate in ModelSim-Altera.
in fact it was what I do.thanks
Honored ContributorMay I recall my first answer to the first of your serial posts:
--- Quote Start --- FPGA PLLs can't generate that low frequencies, check the respective device handbooks for the available PLL frequency range. Also CPLDs have no PLL hardware. A clock divider is the usual solution for low frequencies. --- Quote End --- As you clearly mentioned MAX CPLD now, we can stop the PLL and altpll Megawizard discussion. The clock generator problem reduces to calculate n in clkoutfreq = clkinfreq / n and build a synchronous counter. The required waveform depends on the intended purpose of your output clocks, they can be e.g. 50% duty cycle or one input clock cycle duration. The latter would be meaningful in a synchronous design, that uses the divided clocks as a clock enable. But you didn't tell and we can't know.Honored Contributorthank you but I want to know by what method it can be done
Honored ContributorUse a counter controlled by a global (fast) clock. Compare to specific values to obtain the desired output clock frequency, and swith the low clock when this value is reached. Reset the counter at the same time and start the process again.
Honored Contributoragree thank you but I want to use a circuit that already exists on the Quartus software and I get code for vhdl simulation in ModelSim Altera
Honored ContributorI don't think that such a component exists in Quartus but it's very straightforward to write in VHDL.
Honored Contributoryes I think with a PLL, using the tools altpll
Honored ContributorThe Max CPLDs don't have PLLs.
Honored ContributorExactly. Cause I already mentioned it twice, I'm tired of the discussion now.
Honored Contributorbut how we can solve this problem
Honored ContributorUsing a counter, as suggested above.
