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Altera_Forum
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17 years ago

clock generator

Thank you, how i do? this is a way to learn . I have a project or I do PRODUCING A synchronous clock generator using Altera CPLD max3, ie from an input clock I must have output frequencies 8kHz outpu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I don't think that such a component exists in Quartus but it's very straightforward to write in VHDL.