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Altera_Forum
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17 years ago

clock generator

Thank you, how i do? this is a way to learn . I have a project or I do PRODUCING A synchronous clock generator using Altera CPLD max3, ie from an input clock I must have output frequencies 8kHz outpu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

May I recall my first answer to the first of your serial posts:

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FPGA PLLs can't generate that low frequencies, check the respective device handbooks for the available PLL frequency range. Also CPLDs have no PLL hardware.

A clock divider is the usual solution for low frequencies.

--- Quote End ---

As you clearly mentioned MAX CPLD now, we can stop the PLL and altpll Megawizard discussion. The clock generator problem reduces to calculate n in clkoutfreq = clkinfreq / n and build a synchronous counter. The required waveform depends on the intended purpose of your output clocks, they can be e.g. 50% duty cycle or one input clock cycle duration. The latter would be meaningful in a synchronous design, that uses the divided clocks as a clock enable. But you didn't tell and we can't know.