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Altera_Forum's avatar
Altera_Forum
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17 years ago

clock generation from FPGA

hi

i want to generate 1300KHz clock with 8MHz input to CYCLONE3.

i want to generate some more clocks which are less than 1KHz and in the range of 100 Hz.

i tried with PLLs IN CYCLONE , but it is not supporting for that low frequencies

can any one help which is the best way to generate using cyclone3

with regards

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    You can use counters to generate such low clk rates. You will then run into issues of gated clk and timing violations even at low clk rates. The best way may be to keep the fast clk to all flips then use your slow clk signals from the counter divisions as enable for these flips.

    edit:

    A neat way is to use modulo adder for counting:

    The adder will run on fast clk(8MHz)

    for example to generate 1300Khz : add 13 modulo 80

    at overflow generate either a pulse(to be used as enable) or toggle a signal(for 50/50 duty cycle clk, this clk wouldn't be always regular but shouldn't matter in most cases)