clock generation from FPGA

You can use counters to generate such low clk rates. You will then run into issues of gated clk and timing violations even at low clk rates. The best way may be to keep the fast clk to all flips then use your slow clk signals from the counter divisions as enable for these flips.

edit:

A neat way is to use modulo adder for counting:

The adder will run on fast clk(8MHz)

for example to generate 1300Khz : add 13 modulo 80

at overflow generate either a pulse(to be used as enable) or toggle a signal(for 50/50 duty cycle clk, this clk wouldn't be always regular but shouldn't matter in most cases)