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Altera_Forum
Honored Contributor
Honored Contributorclock gating in FPGA
Hi,
I want to do clock gating in a design targetted for FPGA. The design was intially build for ASIC which have custom clock gating cells (latch based). I need to synthesize this design in Altera Stratix FPGA. Should i replace this clock gating cells with FPGA clock gating cells. If yes, please let me know how to take this forward. Regards, freak3 Replies
Altera_ForumJust check the user guide
http://www.altera.com/literature/ug/ug_altclock.pdf- Altera_Forum
Hi,
Thanks for the reply. Can you please share the rtl, or please let me know from where can i get this code. Regards, Jaseel - Altera_Forum
Yes, you should.
In Altera FPGAs, use a ALT_CLKCTRL block for clock gating or clock multiplexing.
