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Altera_Forum
Honored Contributor
Honored Contributorclock gating in FPGA
Hi, I want to do clock gating in a design targetted for FPGA. The design was intially build for ASIC which have custom clock gating cells (latch based). I need to synthesize this design in ...
Altera_ForumHonored Contributor
Honored ContributorYes, you should.
In Altera FPGAs, use a ALT_CLKCTRL block for clock gating or clock multiplexing.
