Clock Frequency Max

Question

Hi, this may be a stupid question so I ask for your forgiveness in advance:

I have an application where I have two square wave inputs at 300 MHz; I wish to measure the time delay between the rising edge of both signals. For this I need to know: what is the maximum clock frequency given by the Cyclone V device? And to what extent can this be increased by built in PLLs? And finally what maximum frequency can the board be reliably and safely be operated at?

Many Thanks,

Numi

altera_forum · Answer

I think the maximum clock rates that can be achieved inside the fpga can be determined from the device's switching characteristics data sheet.  You say you want to measure the time delay between 2 rising edges...the resolution you will achieve will be a function of your sampling clock.  Without checking the data sheets, I would think that the 300 MHz input frequencies doesn't give you a lot of options in terms of how fast you can run your sampling clock for a desired resolution.  300 MHz is a pretty brisk input rate, especially for a Cyclone 5 part.

altera_forum · Answer

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I have an application where I have two square wave inputs at 300 MHz; I wish to measure the time delay between the rising edge of both signals.

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First question; why?

Clarification; if you are expecting to measure the delay between the edges of the two signals, then they must be synchronous. If the signals are synchronous, then chances are you do not need to align the clock edges, you just need to use FIFOs to move data between the common synchronous clock domains.

If you absolutely have to measure the phase delay, then one way is to use a phase-detector. A "simple" phase-detector can be constructed using high-speed (external) XOR gate followed by a low pass filter. The DC output of that filter represents the phase difference between the two clocks. Depending on your application, this may be sufficient.

Cheers,

Dave

altera_forum · Answer

The method of xor suggested by Dave should be ok for phase difference.

Another draconian method to measure absolute delay is to have two FIR filters of same coefficients (just any symmetric set). Then run each FIR on its clock using impulse input. Measure the delay of peaks e.g. in the scope.

altera_forum · Answer

I'm sorry, the input frequencies are maxed at 300 kHz not MHz. I assume I can use the above suggested methods to even greater effect given this change? As for why, because my professor cannot come up with a more creative assignment. Thanks guys!!!

altera_forum · Answer

And the signals have the same period/frequency, identical characteristics in every way except that one leads the other

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Clock Frequency Max

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