Clock Frequency Max

since it is 300KHz then you don't need much work. you can use simple counters or state machine but I have done a design before based on the following approach:

1) register both inputs twice on your clock

in1 => in1_1d => in1_2d

in2 => in2_1d => in2_2d

2) run two flips one clocked by in1 and one clocked by in2

if in1 edge arrives set flip1 output to '1'

if in2 edge arrives set flip2 output to '1';

and apply async reset if both these outputs are '1'; (this will be a short glitch but should do)

3) run two counters on your system clk

count1 enabled if flip1 output = '1

count2 enabled if flip2 output = '1'

asynchronously reset both counters if in1_2d = '1' and in2_2d = '1';

4) assign delay as signed value

if count1 > count2 then it is +count1

else it is minus count2