Clock Frequency Max

I think the maximum clock rates that can be achieved inside the fpga can be determined from the device's switching characteristics data sheet. You say you want to measure the time delay between 2 rising edges...the resolution you will achieve will be a function of your sampling clock. Without checking the data sheets, I would think that the 300 MHz input frequencies doesn't give you a lot of options in terms of how fast you can run your sampling clock for a desired resolution. 300 MHz is a pretty brisk input rate, especially for a Cyclone 5 part.