Forum Discussion
EugenyB
Occasional Contributor
Occasional ContributorClock enable for connected module not having it
Consider the following code:
reg [1:0] div = {2{1'b0}};
always@(posedge clock)
div[1:0] <= div[1:0] + 1'b1;
wire clk_enable = (div[1:0] == 2'b00);
always@(posedge clock or nege...
RichardT_altera
Super Contributor
Super ContributorI have yet to receive any response from you but I believed that you have found a solution to your question.
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
