EugenyB
Occasional Contributor
Occasional ContributorClock enable for connected module not having it
Consider the following code:
reg [1:0] div = {2{1'b0}};
always@(posedge clock)
div[1:0] <= div[1:0] + 1'b1;
wire clk_enable = (div[1:0] == 2'b00);
always@(posedge clock or nege...
