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EugenyB

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Re: Can not make PLL dynamic reconfiguration (without ALTPLL_RECONFIG)
I found the solution to the problem. Information is buried in ALTPLL and ALTPLL_RECONFIG documents in different places, people who do not have deep overview of the architecture would hardly match different, but related pieces of info. For cyclone 3 I must activate PLL areset pin for one reconfig clock cycle after PLL raises scandone.
4 years ago Place FPGA Device
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Re: Can not make PLL dynamic reconfiguration (without ALTPLL_RECONFIG)
I have made design using ALTPLL_RECONFIG and its simulation behaves the same erratic way - scandone goes high and does not get back low - with busy stuck high.
4 years ago Place FPGA Device
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Re: Createa range of clock frequencies
Hello Ash, thank you very much for reply. Have seen these documents, and also found one implementation example. Already built a prototype. Of course made some mistakes, but there's a problem which I can not solve, I created another post for it. Everything seems to work properly except scandone does not go low after reconfiguration. At the same time it reconfigures properly with scandone high - my testbench reconfigures PLL every ~3 seconds to new frequency - frequency locks but scandone is always high.
4 years ago Place FPGA Device
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Re: Can not make PLL dynamic reconfiguration (without ALTPLL_RECONFIG)
Found the problem for wrong frequency. I was shifting bit 0 first. Manual says it must be bit 143 first. Kind of against logic, but why not. However scandone is still always high after first reconfiguration. At the same time PLL locks, and everything else seems to be ok. Checked with scope, output frequencies are correct. Tried Modelsim (it is stupid not loading MIF files - thus used scan chain filled with 0s) - it also shows scandone going up and never getting low, however manual says that it must deactivate as soon as reconfiguration is complete. Above shows the completion of the scan line write and reconfiguration The above shows whole operation. I managed to load proper .HEX file into ROM in Modelsim, and as we see `scandone` goes high and does not fall back low in simulation (as well as in real system). Lock goes high in some time (not shown on the picture). You can see that c4-c1 are loaded with zero counters, only c0 is being initialized. Above picture: putting same "valid" settings to all the PLL channels does not make difference - scandone still does not return low. Unfortunately the list of registers above does not have any enable/disable bits for specific PLL outputs (like we have checkmarks in megawizard). May loading zeroes into the counter prevent scandone to complete? Can not get what I am doing wrong here.
4 years ago Place FPGA Device
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Can not make PLL dynamic reconfiguration (without ALTPLL_RECONFIG)
Using Cyclone 3 and Quartus 13.1. The result is PLL changes clock speed to wrong value (much slower that should be), scandone goes high, and PLL does not lock. What I do: 1. In megawizard configure PLL the way I need, save it, open it again in megawizard, and use "generate configuration file" having MIF file created for present configuration. 2. When reconfiguration is needed I shift 144 bits in the order from 0 to 143 (as in MIF file), through scandata, clock is controlled by scanclkena. 3. Wait one reconfiguration clock cycle, and activate configupdate for one clock cycle. 4. independently of actions above watch for scandone, and on second clock after its falling edge reset PLL using areset having it active for one clock cycle. What is wrong? I checked shifting data in correct direction from bit 0 to 143, I checked it takes 144 cycles to shift, thus data must be in PLL. But still it starts with wrong frequency and never gets done.
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4 years ago Place FPGA Device
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Re: Createa range of clock frequencies
The better way seems to be design my own simple reconfig circuit basing on ROM of 16*16*9 bit size feeding the PLL. I will design the script converting bit-based MIF configuration files created using megawizard to this ROM image.
4 years ago Place FPGA Device
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Re: Createa range of clock frequencies
It seems the right way is to use ALTPLL_RECONFIG with ROM containing 16 sets for the PLL (4096*1 M9K ROM block). Am I correct? Any better way?
4 years ago Place FPGA Device
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Createa range of clock frequencies
I am using Cyclone 3 chip, it has 2 PLLs and a number of clock controllers. Is it possible to have any combinations of above features (or employing any other) and have FPGA clocking circuit output frequencies from 72 to 100 MHz in 2 MHz step (therefore 72, 74, 76, 78, 80 ... 96, 98, 100 MHz) selectable by some vector [3:0]? Frequencies need not be 100% exact (but accurate + global), these frequencies will be used for another circuit to train its communication channel and find maximal possible frequency channel survives with.
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4 years ago Place FPGA Device
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Re: Clock enable for connected module not having it
I decided to go the other route changing the architecture rather than considering more and more complex clocking problem. Now I use one control signal using synchronizer, and ensure that data is held several cycles after synchronizer finishes to ensure set up and hold times are not violated when circuit driving remote update latches the data. Thanks for your help.
4 years ago Place FPGA Device
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Re: Clock enable for connected module not having it
The things may be more complicated than I thought before. Analyzing the remote update block documentation I do not see any specification for the clock. I see only clock speed up to 40 MHz and that it must be "valid". Nothing about clock duty cycle. And unfortunately, implementing the clocking using clock enable turns clock to duty cycle other than 50%, and pulse width will be the same as original clock at 120 MHz. Within the "remote_update" module clock connects to "cycloneiii_rublock", and I can not find any information on it.
4 years ago Place FPGA Device
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