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EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Createa range of clock frequencies

I am using Cyclone 3 chip, it has 2 PLLs and a number of clock controllers.

Is it possible to have any combinations of above features (or employing any other) and have FPGA clocking circuit output frequencies from 72 to 100 MHz in 2 MHz step (therefore 72, 74, 76, 78, 80 ... 96, 98, 100 MHz) selectable by some vector [3:0]? Frequencies need not be 100% exact (but accurate + global), these frequencies will be used for another circuit to train its communication channel and find maximal possible frequency channel survives with.

  • Ash_R_Intel's avatar
    Ash_R_Intel
    4 years ago

    Hi Eugeny,

    The other thread that you mentioned related to Scandone not going low was resolved by usage of areset signal. You seems to have figured that out yourself.


    If so, can this thread be also considered as resolved?


    Regards


5 Replies

  • EugenyB's avatar
    EugenyB
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    It seems the right way is to use ALTPLL_RECONFIG with ROM containing 16 sets for the PLL (4096*1 M9K ROM block). Am I correct? Any better way?

    • EugenyB's avatar
      EugenyB
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      The better way seems to be design my own simple reconfig circuit basing on ROM of 16*16*9 bit size feeding the PLL. I will design the script converting bit-based MIF configuration files created using megawizard to this ROM image.

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    You may want to refer the following two documents:

    1) Cyclone® III Device Handbook - Page 86 onwards

    2) AN507: Link provided in the Handbook, page 90.


    Regards


    • EugenyB's avatar
      EugenyB
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Hello Ash, thank you very much for reply. Have seen these documents, and also found one implementation example. Already built a prototype. Of course made some mistakes, but there's a problem which I can not solve, I created another post for it. Everything seems to work properly except scandone does not go low after reconfiguration. At the same time it reconfigures properly with scandone high - my testbench reconfigures PLL every ~3 seconds to new frequency - frequency locks but scandone is always high.

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Eugeny,

    The other thread that you mentioned related to Scandone not going low was resolved by usage of areset signal. You seems to have figured that out yourself.


    If so, can this thread be also considered as resolved?


    Regards