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EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Createa range of clock frequencies

I am using Cyclone 3 chip, it has 2 PLLs and a number of clock controllers. Is it possible to have any combinations of above features (or employing any other) and have FPGA clocking circuit output...
  • Ash_R_Altera's avatar
    Ash_R_Altera
    4 years ago

    Hi Eugeny,

    The other thread that you mentioned related to Scandone not going low was resolved by usage of areset signal. You seems to have figured that out yourself.


    If so, can this thread be also considered as resolved?


    Regards


Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

You may want to refer the following two documents:

1) Cyclone® III Device Handbook - Page 86 onwards

2) AN507: Link provided in the Handbook, page 90.


Regards


EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello Ash, thank you very much for reply. Have seen these documents, and also found one implementation example. Already built a prototype. Of course made some mistakes, but there's a problem which I can not solve, I created another post for it. Everything seems to work properly except scandone does not go low after reconfiguration. At the same time it reconfigures properly with scandone high - my testbench reconfigures PLL every ~3 seconds to new frequency - frequency locks but scandone is always high.