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EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Createa range of clock frequencies

I am using Cyclone 3 chip, it has 2 PLLs and a number of clock controllers. Is it possible to have any combinations of above features (or employing any other) and have FPGA clocking circuit output...
  • Ash_R_Altera's avatar
    Ash_R_Altera
    4 years ago

    Hi Eugeny,

    The other thread that you mentioned related to Scandone not going low was resolved by usage of areset signal. You seems to have figured that out yourself.


    If so, can this thread be also considered as resolved?


    Regards


EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

It seems the right way is to use ALTPLL_RECONFIG with ROM containing 16 sets for the PLL (4096*1 M9K ROM block). Am I correct? Any better way?

  • EugenyB's avatar
    EugenyB
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    The better way seems to be design my own simple reconfig circuit basing on ROM of 16*16*9 bit size feeding the PLL. I will design the script converting bit-based MIF configuration files created using megawizard to this ROM image.