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EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
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Can not make PLL dynamic reconfiguration (without ALTPLL_RECONFIG)

Using Cyclone 3 and Quartus 13.1. The result is PLL changes clock speed to wrong value (much slower that should be), scandone goes high, and PLL does not lock. What I do: 1. In megawizard con...
  • EugenyB's avatar
    EugenyB
    4 years ago

    I found the solution to the problem. Information is buried in ALTPLL and ALTPLL_RECONFIG documents in different places, people who do not have deep overview of the architecture would hardly match different, but related pieces of info. For cyclone 3 I must activate PLL areset pin for one reconfig clock cycle after PLL raises scandone.

EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

I have made design using ALTPLL_RECONFIG and its simulation behaves the same erratic way - scandone goes high and does not get back low - with busy stuck high.

EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

I found the solution to the problem. Information is buried in ALTPLL and ALTPLL_RECONFIG documents in different places, people who do not have deep overview of the architecture would hardly match different, but related pieces of info. For cyclone 3 I must activate PLL areset pin for one reconfig clock cycle after PLL raises scandone.