Clock division with altera max-10m50d

hi,

I'm new to the world of FPGA and VHDL.. literally it is way more tough to understand then the msp micro controllers and embedded C

recently started programing with the @altera-max10 (10M50DAF484C6GES) with Quartus prime lite edition 20.1version

I'm trying to implement clock division.. after implementing few basic programs

Simulation was happening but when i upload code in the hardware it is not even working

also all pins are in 2.5V.. I'm using a THDG-HTG (HSMC Connector)..

Kindly help me..

Best regards,

Tex