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Tex's avatar
Tex
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Clock division with altera max-10m50d

hi,

I'm new to the world of FPGA and VHDL.. literally it is way more tough to understand then the msp micro controllers and embedded C

recently started programing with the @altera-max10 (10M50DAF484C6GES) with Quartus prime lite edition 20.1version

I'm trying to implement clock division.. after implementing few basic programs

Simulation was happening but when i upload code in the hardware it is not even working

also all pins are in 2.5V.. I'm using a THDG-HTG (HSMC Connector)..

Kindly help me..

Best regards,

Tex

Configuration
Generic Io
  • Tex's avatar
    Tex
    2 years ago

    we can use only clock_out pins mentioned in the HSMC schematic..

    i was using gpio pins for the clock output..

    now it is working fine

3 Replies

  • Tex's avatar
    Tex
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Yes it is working

  • Tex's avatar
    Tex
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    we can use only clock_out pins mentioned in the HSMC schematic..

    i was using gpio pins for the clock output..

    now it is working fine