Clock Divider

Neither.

Either use:

1. use Phase lock loops instead. Logic generated clocks will give you large skew and you'll have all sorts of failures.

2. Instead of using your outputs from your counters as clocks, use them as enables on registers running at sampling frequency.

1. My input clock rate can't fullfill the requirement of pll.

2. Yes, i am using this method. However, the structure can be different as i mentioned.

Hi,

1) It doesn't work as expected :

- if (count == 2, 4, 6, 8, ...) a = 1;//64*Fs

- else if (count == 4, 8, 12,...) b =1; //32*Fs // count == 4,8 already done in the above condition.

2)too numerous counters

I give a 3rd solution : one counter (range 5 downto 0 for example) and take each bit that switches on divided frequence :

count(0) for signal f/2,

count(1) for f/4,

count(2) for f/8

....

May it help you !

EDIT :

I see you need F/6 for example : take a counter modulo 6

F/12 take (F/6)/2 : be aware about their "phase".