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Altera_Forum
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16 years ago

Clock Divider

I have a input clock 128*Fs(Sampling Frequency). I need derived clocks of Fs, 2Fs, 4Fs, 8Fs, 16Fs ... 64Fs. However, there are 2 ways in my mind to implement it. 1st: 1 module only an...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Neither.

Either use:

1. use Phase lock loops instead. Logic generated clocks will give you large skew and you'll have all sorts of failures.

2. Instead of using your outputs from your counters as clocks, use them as enables on registers running at sampling frequency.